This application claims the priority benefit of Taiwan application serial no. 91113450, filed Jun. 20, 2002.
1. Field of Invention
The present invention relates to a current-amplifying logarithmic mode CMOS image sensor. More particularly, the present invention relates to a current-amplifying logarithmic mode CMOS image sensor having a lateral bipolar transistor structure.
2. Description of Related Art
In recent years, CMOS image sensors have been widely used in closed-circuit monitor systems, video communicators, digital cameras, fingerprint identification systems and so on. Some of the reasons for the popularity of CMOS image sensors include a low operation voltage and minimal power consumption. Moreover, CMOS circuits can be easily integrated (that is, control logic, logic/digital conversion circuit can be fabricated on a single chip), random accessed and fabricated by using conventional CMOS manufacturing techniques.
A current-amplifying logarithmic mode CMOS image sensor is one type of CMOS image sensor. FIG. 1 is the schematic circuit diagram of a conventional logarithmic mode CMOS image sensor. As shown in FIG. 1, the logarithmic mode CMOS image sensor mainly includes three NMOS transistors 101, 103, 105 and a photodiode 107. The gate of the NMOS transistor 101 is tied to a terminal connecting the highest voltage Vdd in the circuit. The voltage between the gate terminal and source terminal of the NMOS transistor 101 has a logarithmic relationship with the current flowing from the drain terminal of the NMOS transistor 101. Hence, the output voltage Vout and the intensity of light illuminating on the photodiode 107 also have a logarithmic relationship. Consequently, the conventional logarithmic mode CMOS image sensor has very wide dynamic range.
Although a conventional logarithmic mode CMOS image sensor has very high sensitivity and switches fast, the photo current flowing through the NMOS transistor 101 is too small when the photodiode 107 is illuminated by light within an ordinary range. This often leads to the output voltage Vout of the conventional logarithmic mode CMOS image sensor being limited to a very small voltage range (between 0.2Vxcx9c0.5V). Hence, analog/digital conversion circuits in a subsequent stage can hardly analyze the output voltage Vout submitted from the conventional logarithmic mode CMOS image sensor. (Because the range of the output voltage provided by the conventional logarithmic mode CMOS image sensor is less than 1V, an 8-bit analog/digital converter needs to distinguish a voltage step as small as 1/256xcx9c0.004V.)
Accordingly, one object of the present invention is to provide a logarithmic mode CMOS image sensor using a lateral bipolar junction structure instead of photodiode for increasing voltage range at the voltage output terminal so that an analog/digital conversion circuit at a subsequent stage is easier to implement. The new design is called current-amplifying logarithmic mode CMOS image sensor.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described, the invention provides a current-amplifying logarithmic mode CMOS image sensor. The CMOS image sensor includes a first MOS transistor, a second MOS transistor, a third MOS transistor and a sensor. The first MOS transistor has a gate terminal, a first connection terminal and a second connection terminal. The gate terminal and the first connection terminal of the first MOS transistor are tied to the highest voltage terminal. The second MOS transistor has a gate terminal, a first connection terminal and a second connection terminal. The gate terminal of the second MOS transistor and the second connection terminal of the first MOS transistor are tied to a node point. The first connection terminal of the second MOS transistor is tied to the highest voltage terminal. The third MOS transistor also has a gate terminal, a first connection terminal and a second connection terminal. The gate terminal of the third MOS transistor is tied to a row select signal. The first connection terminal of the third MOS transistor is tied to the second connection terminal of the second MOS transistor. In addition, the second terminal of the third MOS transistor serves as a voltage output terminal. Ibias is the column amplifier bias current. Ibias has the first and terminal. The first terminal of Ibias is connected to the second terminal of the third MOS. The sensor includes a PMOS transistor and a lateral bipolar junction transistor. The PMOS transistor has a gate terminal, a first connection terminal and a second connection terminal. The first connection terminal of the PMOS transistor is connected to the node point and the second connection terminal of the PMOS transistor is connected to a ground terminal. The gate terminal of the PMOS transistor is tied to a terminal for receiving a voltage control signal. The emitter terminal of the lateral PNP bipolar junction transistor is connected to the node point and the collector terminal of the lateral PNP bipolar junction transistor is connected to the ground terminal. The base terminal of the lateral PNP bipolar junction transistor remains in a floating state.
This invention also provides a sensing device for a current-amplifying logarithmic mode CMOS image sensor. The sensing device comprises a substrate, a well, a first injection region, a second injection region, a third injection region, and a gate. The well doped with dopants that have different conductive type from the substrate is embedded within the substrate. The first injection region includes a connection terminal having ionic dopants that differ from the well. The first injection region is embedded within the well. The connection terminal is connected to a ground terminal. The second injection region includes a connection terminal having ionic dopants identical to the first injection region. The second injection region is embedded within the well, separated from but adjacent to the first injection region. The connection terminal of the second injection region is tied to the source/drain connection terminal of a load transistor, that is, the first MOS transistor within the current-amplifying logarithmic mode CMOS image sensor. The third injection region contains ionic dopants identical to the one within the well. The third injection region is embedded within the well, separated from but adjacent to the first and the second injection region. The gate is formed in the region above the space between the first injection region and the second injection region. The gate controls junction conductance between the first injection region, the well and the second injection region
Note that adjusting width/length ratio of the load transistor (the first MOS transistor) can provide a large voltage output range to the current-amplifying logarithmic mode CMOS image sensor.
In brief, the current-amplifying logarithmic mode CMOS image sensor uses a bipolar junction transistor instead of a conventional photodiode. By adjusting the width/length ratio of a load transistor (that is, the first MOS transistor) of the sensing device within the current-amplifying logarithmic mode CMOS image sensor, image contrast is improved and output voltage range is increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.